EEPROM and Flash memories (NOR and NAND) use a floating gate (FG) to store charges, which represent information. These memory devices suffer from degradation mechanisms after program/erase cycles. They also suffer from erratic erase of memory cells. The specific matrix architecture of NAND Flash leads to more “read disturb” errors than NOR Flash. A “read disturb” occurs when the amount of charge in a memory cell is altered by reading another cell, physically close to or sharing control lines with the disturbed cell. A single read disturb event may not produce enough change in charge content to effect an error, but cumulative read disturbs may eventually do so.
Scaling of technology and the interest in storing more than one bit per cell for increased storage density requires tighter fabrication and operation tolerances. The recognition that ever denser EEPROM and Flash memories need to address unavoidable occasional bit errors led to solutions including error correcting codes.
Multi-Level Cell (MLC) Flash devices can store multiple bits per memory cell by charging the floating gate of a transistor to different selected threshold voltage (VT) levels and, thereby, use the analog characteristic of the cell in mapping a bit pattern to a specific voltage level. In the case of NAND Flash, the VT of MLC devices are, conceptually, read by sequentially applying selected read voltage (VREAD) levels to the floating gates of the cells. Typically, the voltage ranges are selected with a guardband between each range to help ensure that the normal VT distributions do not overlap.
In NOR Flash, cells are connected in parallel to the bitlines, which allows cells to be individually read and programmed.
Published U.S. patent application 20080307270 by Tieniu Li (Dec. 11, 2008) describes a scheme implemented on a host device for detection of emerging bad blocks in a NAND that includes keeping at least a partial history of errors during read operations.
Published U.S. patent application 20100214847 by Nishihara, et al. describes a NAND Flash memory system that is said to reduce variations in the read disturb characteristic from chip to chip by that including a peripheral circuit that includes means for storing and retrieving a corrected read voltage for use by a memory controller. The memory controller performs data input/output control and data management on the Flash memory, adds error correction codes (ECC) upon writing, and analyzes the error correction codes upon reading.
Given that degradation of memory content is progressive and unavoidable with time and number of program/erase cycles, there is a need for an early warning system that detects degradation while data is still correctly being read and mitigating actions can be taken without data loss. Such a system can stand alone or be complementary to error correcting schemes to further increase reliability and operational life of EEPROM and Flash memories.